From: Tulio A M Mendes <tadryanom@hotmail.com>
Date: Thu, 12 Feb 2026 06:42:19 +0000 (-0300)
Subject: refactor: extract x86 GDT/GS TLS setup from scheduler to HAL layer
X-Git-Url: https://projects.tadryanom.me/docs/static/git-favicon.png?a=commitdiff_plain;h=a2248e0fbb1849f60b01107a9858e4694e54ce6e;p=AdrOS.git

refactor: extract x86 GDT/GS TLS setup from scheduler to HAL layer

Added hal_cpu_set_tls(base) to the HAL CPU API with x86 implementation
(GDT entry 22 + GS segment load) and a no-op fallback for other arches.

kernel/scheduler.c no longer contains x86 inline assembly for TLS —
the #if defined(__i386__) block is replaced by a single HAL call.
---

diff --git a/include/hal/cpu.h b/include/hal/cpu.h
index dcb196d..1ad85a8 100644
--- a/include/hal/cpu.h
+++ b/include/hal/cpu.h
@@ -15,4 +15,6 @@ void hal_cpu_idle(void);
 
 uint64_t hal_cpu_read_timestamp(void);
 
+void hal_cpu_set_tls(uintptr_t base);
+
 #endif
diff --git a/src/hal/x86/cpu.c b/src/hal/x86/cpu.c
index 1adc72e..d863996 100644
--- a/src/hal/x86/cpu.c
+++ b/src/hal/x86/cpu.c
@@ -54,6 +54,15 @@ uint64_t hal_cpu_read_timestamp(void) {
     return ((uint64_t)hi << 32) | lo;
 }
 
+void hal_cpu_set_tls(uintptr_t base) {
+    /* GDT entry 22: user TLS segment (ring 3, data RW) */
+    gdt_set_gate_ext(22, (uint32_t)base, 0xFFFFF, 0xF2, 0xCF);
+    __asm__ volatile(
+        "mov $0xB3, %%ax\n"
+        "mov %%ax, %%gs\n" : : : "ax"
+    ); /* selector = 22*8 | RPL=3 = 0xB3 */
+}
+
 #else
 
 uintptr_t hal_cpu_get_stack_pointer(void) {
@@ -85,4 +94,8 @@ uint64_t hal_cpu_read_timestamp(void) {
     return 0;
 }
 
+void hal_cpu_set_tls(uintptr_t base) {
+    (void)base;
+}
+
 #endif
diff --git a/src/kernel/scheduler.c b/src/kernel/scheduler.c
index e6cc36e..7a5d326 100644
--- a/src/kernel/scheduler.c
+++ b/src/kernel/scheduler.c
@@ -434,18 +434,9 @@ static void clone_child_trampoline(void) {
     }
 
     /* Load user TLS into GS if set */
-#if defined(__i386__)
     if (current_process->tls_base) {
-        extern void gdt_set_gate_ext(int num, uint32_t base, uint32_t limit,
-                                      uint8_t access, uint8_t gran);
-        /* Use GDT entry 22 as the user TLS segment (ring 3, data RW) */
-        gdt_set_gate_ext(22, (uint32_t)current_process->tls_base, 0xFFFFF, 0xF2, 0xCF);
-        __asm__ volatile(
-            "mov $0xB3, %%ax\n"
-            "mov %%ax, %%gs\n" : : : "ax"
-        ); /* selector = 22*8 | RPL=3 = 0xB3 */
-    }
-#endif
+        hal_cpu_set_tls(current_process->tls_base);
+    }
 
     hal_usermode_enter_regs(&current_process->user_regs);
 }