feat: improve spinlock with per-arch cpu_relax() and memory barriers

feat: improve spinlock with per-arch cpu_relax() and memory barriers

Spinlock improvements for SMP readiness:
- Add cpu_relax() with per-arch spin-wait hints:
  x86: PAUSE, ARM/AArch64: YIELD, RISC-V: FENCE, MIPS: PAUSE
- Add __sync_synchronize() barrier before lock release in spin_unlock
- Add spin_is_locked() debug helper
- Add spin_trylock() for non-blocking lock attempts
- TTAS (test-and-test-and-set) pattern with cpu_relax() in inner loop
- __sync_lock_test_and_set maps to XCHG (x86), LDREX/STREX (ARM),
  AMOSWAP.W.AQ (RISC-V), LL/SC (MIPS)

Passes: make, cppcheck, QEMU smoke test.