feat: Fase 9 — ATA Bus Master IDE DMA for read/write

feat: Fase 9 — ATA Bus Master IDE DMA for read/write

Implement Bus Master IDE DMA as a transparent upgrade over PIO:

- New ata_dma.c: Bus Master IDE DMA driver for PIIX3 IDE controller
  - Finds IDE controller via PCI class 0x01:0x01
  - Reads BAR4 for Bus Master I/O base, enables PCI bus mastering
  - Allocates PRDT and bounce buffer pages at dedicated VAs
    (0xC0220000/0xC0221000) to avoid heap VA collisions
  - Polling-based DMA completion (BSY clear + BM Active clear)
  - IRQ 14 handler with dma_active flag to prevent race between
    IRQ handler and polling loop on ATA status register
  - spin_lock (not irqsave) for serialization — PIIX3 requires
    interrupt delivery for DMA completion signaling

- Modified ata_pio.c: transparent DMA upgrade
  - ata_pio_init_primary_master registers IRQ 14 handler early
    (before IDENTIFY) to prevent INTRQ storm
  - Calls ata_dma_init after IDENTIFY to probe for DMA capability
  - ata_pio_read28/write28 delegate to DMA when available,
    fall back to PIO if DMA init failed

- New include/ata_dma.h: public API header

Key bugs fixed during development:
- hal_mm_phys_to_virt can map PMM pages into heap VA range
  (phys 0x10000000 -> virt 0xD0000000 = heap base) — use
  dedicated VAs instead
- ATA INTRQ must be deasserted by reading status register;
  without IRQ handler, unacknowledged INTRQ causes interrupt storm
- nIEN must be cleared before DMA so device asserts INTRQ
- DMA direction bit must be set before Start bit per ATA spec

Tested: 4-CPU (25s) and 1-CPU (45s) pass all init.elf tests
including diskfs getdents and /persist/counter.